The central processing unit (CPU) or processor lies at the heart of all modern computing systems. The processor executes instructions of a computer program and thus enables the computer perform useful work—in whatever form that work may take. CPUs are prevalent in all forms of digital devices in modern life and not just dedicated computing machines such as personal computers, laptops and PDAs. Modern microprocessors appear in everything from automobiles to cellular telephones to children's toys. In modern computing systems, additional hardware may be provided alongside or within the CPU to perform arithmetic operations as part of the computing system's work. Such hardware may comprise an integer unit (IU) for performing integer operations, and/or a floating point unit (FPU) for performing floating point operations.
A problem arises in that program code which is executable by one type of processor often cannot be executed in any other type of processor, because each type of processor has its own unique Instruction Set Architecture (ISA). Hence, program code conversion has evolved to automatically convert program code written for one type of processor into code which is executable by another type of processor, or to optimise old, inefficient code into a newer, faster version for the same type of processor. That is, in both embedded and non-embedded CPUs, there are predominant ISAs for which large bodies of software already exist that could be “accelerated” for performance or “translated” to other processors that present better cost/performance benefits. One also finds dominant CPU architectures that are locked in time to their ISA and cannot evolve in performance or market reach. This problem applies at all levels of the computing industry, from stand-alone pocket-sized computing devices right through to massive networks having tens or hundreds of powerful servers.
As background information in this field of program code conversion PCT publication WO2000/22521 entitled “Program Code Conversion”, WO2004/095264 entitled “Method and Apparatus for Performing Interpreter Optimizations during Program Code Conversion”, and WO2004/097631 entitled “Improved Architecture for Generating Intermediate Representations for Program Code Conversion”, which are all incorporated herein by reference, disclose methods and apparatus to facilitate such program code conversion capabilities as may be employed in the example embodiments discussed herein.
During program code conversion, one particular problem area concerns the handling of numerical values expressed in floating point notation. Original program code (here called “subject code”) that has been written according to a particular type of processor expects a particular type of execution environment. In particular, the subject code expects hardware support for operations on numerical values expressed in floating point notation to a particular level of numerical precision. This hardware support is provided by a subject FPU.
However, during program code conversion, subject code is converted into target code which is executed on a target computing platform. The target computing platform may comprise a FPU which supports operations on numerical values at a lower precision than those supported by the subject FPU. In this situation there is a fundamental hardware incompatibility between the subject computing platform and the target computing platform.
In response to the above-mentioned problem, PCT publication WO2005/003959 describes a mechanism for performing floating point operations on a target computing platform using a combination of the target FPU and integer hardware on the target computing platform. However, employing a mechanism which uses the integer hardware on the target computing system to provide the results of floating point operations is typically slow.
Therefore, during program code conversion two problems are encountered. Firstly, there is a problem that the hardware of the target computing platform may not provide floating point hardware support for the level of precision which is expected by the subject code. Secondly, there is the problem that using integer hardware of the target computing platform to provide the results of floating point operations at a precision expected by the subject code, and higher than supported by the target FPU is likely to be inefficient.
These and other problems of the prior art are addressed by the exemplary embodiments of the present invention as will be discussed in more detail below.